1. Field of the Invention
The invention relates to a device for generating bus transactions and responses, and more specifically, to a bus transaction/response generator that creates user-specified bus cycles under high level language control.
2. Description of Related Art
FIG. 1 illustrates a portion of a typical computer system, such as a personal computer (PC), including one or more processors 10 and a chipset 12 coupled together by means of a processor bus 14. The chipset 12 is coupled to a memory device 15 such as a dynamic random access memory (DRAM) device and an input/output (I/O) bus 16.
The processor 10 is the “brains” of the computer. The processor 10 includes an arithmetic logic unit (ALU), which performs arithmetic and logical operations and a control unit, which extracts instructions from memory and decodes and executes them, calling on the ALU when necessary. A symmetric system is a system that includes multiple processors, wherein each of the processors is capable of executing any task.
A bus is like a highway on which data travel within a computer. It is simply a channel over which information flows between two or more devices. A bus normally has access points, or places into which a device can tap to become attached to the bus, and devices on the bus can send to, and receive information from, other devices. The processor bus 14 is the bus that the chipset 12 uses to send information to and from the processor 10. Computer systems also typically include at least one I/O bus 16, such as a peripheral component interconnect (PCI) bus, which is generally used for connecting performance-critical peripherals to the memory 15, chipset 12, and processor 10. For example, video cards, disk storage devices, high-speed networks interfaces generally use a bus of this sort. PCs typically also include additional I/0 buses, such as an industry standard architecture (ISA) bus, for slower peripherals such as mice, modems, regular sound cards, low-speed networking, and also for compatibility with older devices.
The system chipset 12 controls this communication, making sure that every device in the system is talking properly to every other device. The chipset 12 is an integrated set of components that perform many of the vital functions of the computer system, including functions that once required several separate chips. Typical functions performed by the chipset 12 include memory controller, which allows the processor 10 to access the computer memory 15; I/O bus bridge, which interfaces the processor bus 14 with other computer buses, such as the PCI or ISA buses; real-time clock (RTC); direct memory access (DMA) controller, which allows system devices to directly access the memory 15 rather than accessing the memory 15 through the processor 10, keyboard controller, mouse controller, etc.
Each transaction initiated on the processor bus 14 goes through three general stages: the arbitration phase, the address phase, and the data phase. For a component, or “agent,” on the bus 14 to initiate a transaction on the bus 14, the agent must obtain “ownership” of the bus 14. This happens during the arbitration phase, where the agent initiating the transaction, known as the requesting agent, signals that it wants to use the bus 14. Once the requesting agent acquires bus ownership, it sends an address out on the bus 14 during the address phase. The other agents on the bus 14 receive the address and determine which of them is the target of the transaction—the target agent. Finally, during the data phase, the requesting agent waits for the target agent to provide the requested read data or to accept the write data.
Bus transactions on more complex buses, such as the Intel® Pentium® Pro bus, include additional phases. The Pentium® Pro bus, for example, includes the following transaction phases: arbitration phase, request phase, error phase, snoop phase, response phase, and data phase. The Pentium® Pro bus is divided into groups of signals that generally correspond to the transaction phases, each of which is only used during the respective phase of a transaction. The operation of the Pentium® Pro bus is explained in detail in Pentium® Pro Processor System Architecture, by Tom Shanley, MindShare, Inc., chapters 8-17, incorporated herein by reference in its entirety.
When a requesting agent wishes to obtain bus ownership to initiate a bus transaction, it arbitrates for ownership of the request signal group. In a symmetric system (a multiple-processor system wherein each processor is capable of handling any task), multiple processors may simultaneously request ownership of the bus. These processors are referred to as symmetric agents, and the process for determining which symmetric agent gets ownership of the bus is known as symmetric arbitration. In comparison, priority agents are agents on the bus that arbitrate for bus ownership by asserting a priority signal.
Once the requesting agent has ownership of the request signal group, it drives a transaction request onto the request signal group during the request phase. A Pentium® Pro processor bus transaction request phase is two clocks in duration. Address, transaction type and other transaction information is output in two packets during the request phase; one packet during each of the two clocks of the request phase. The other bus agents receive the transaction request and determine which of them is the target agent.
Moreover, specific bus transactions may take a relatively long time to complete. For instance, the target agent may be busy and therefore, not available to immediately complete the request. In this case, the target agent may choose to defer the transaction request to a later time, in which case the target agent is called a deferring agent. Further, data reads and writes may often take a significant amount of time to complete. The Pentium® Pro bus is designed to prevent busy or slow bus agents from tying up the bus for an extended time period. If the target of a data read or write will take a long time to complete the data transfer, it instructs the requesting agent to terminate the transaction, then the targeted agent will initiate a transaction to transfer the data when the read or write is completed.
During the error phase, the bus agents receiving the transaction request inspect the request to determine whether it was corrupted during the transmission by verifying the transaction request's parity bit. Any of the receiving agents that detect a parity error assert the error phase signal. The requesting agent checks the error phase signal at the end of the error phase to see if the request was received without error. If an error was detected, the remaining transaction phases are canceled and the transaction may be retried. If the receiving agents all receive the request without error, the requesting agent proceeds to the next phase.
If the initiated transaction is a memory transaction, agents receiving the transaction request that have an internal cache perform a cache lookup, or “snoop,” to determine whether the requested memory line is in any agent's cache. These agents are referred to as snooping agents. Snooping agents provide the snoop results via the snoop phase signals. During the snoop phase, the requesting agent and the response agent sample the snoop phase signals. Once the snoop phase is complete, the requesting agent proceeds to the response phase and begins sampling the response phase signals. The response agent notifies the requesting agent how it intends to handle the request via the response phase signals.
Finally, if the transaction involves a data transfer, the requesting agent continues with the data phase. If the bus transaction is a data write transaction, the requesting agent delivers the data to the response agent during the data phase. If it is a data read transaction, the response agent delivers the data to the requesting agent. The bus transaction is complete when the data phase is finished.
The Pentium® Pro bus is designed to allow various phases of several different bus transactions to occur simultaneously to improve bus performance. When a request agent finishes with the signal group for a specific phase, it relinquishes control of that signal group and takes ownership of the signal group for the next phase. For example, once the request agent has issued its transaction request and is ready to check the error phase signals, it no longer requires the use of the request phase signals. Thus, it relinquishes control of the request phase signals and allows another bus agent to take control and initiate a transaction.
Components, such as processors and chipsets, coupled to complex buses often contain bugs that cause them to fail during operation. In the failing scenarios, the components frequently respond incorrectly to specific bus transaction sequences, even when the bus transaction sequence is “legal”; in other words, there is nothing in the bus transaction sequence that should have caused the component to fail. The process of correcting these bugs requires inducing the failure under controlled conditions to isolate the bug. Part of this process may require repeating the bus transaction sequence corresponding to the failure.
Current practices for validating bus/component interactions in which failures occur may include operating a processor on a bus using standard assembly language to generate bus transactions. Assembly language, however, has little correlation to the types of bus transactions being generated, offers little control over the exact sequence of bus cycles produced, and offers almost no control over the relative timing between back to back bus transaction phases.
Moreover, this problem is compounded when one or more out-of-order processors are bus agents. An in-order processor fetches a set of instructions and executes them in a sequential program order. On the other hand, an out-of-order processor improves instruction execution performance by executing instructions that are ready for execution before instructions that are not ready, even if the ready instruction is later in the instruction sequence. This prevents the processor from stalling while an instruction is made ready for execution. For example, a non-ready instruction awaiting data from a memory read does not stall the execution of later instructions in the instruction stream that are ready to execute. Thus, with prior art assembly language controlled, processor-generated bus transactions using an out-of-order processor, the processor controls the bus transaction sequences, rather than a technician attempting to generate a specific sequence of bus transactions.
A similar problem occurs in the development of components such as chipsets and processors. In the early design stages, the components being developed are simulated in a software environment and are often driven by a high-level bus model known in the art as a bus functional model (BFM). A simulation stimulus software language may then be used to exercise the simulated system. While these methods provide a designer a high level of control, observability and repeatability when testing system designs, the simulation environments are extremely slow, typically operating at about 1-10 Hz. Further, there is no corresponding capability for repeating the simulation on actual systems (hardware) during the design stages that provides the desired control, observability, and repeatability.
Thus, a need exists for a system that generates precisely controlled, user-specified bus transactions at an acceptable speed.